English translation for "cache coherence"
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- 高速缓存相干
高速缓存一致性
Related Translations:
- Example Sentences:
| 1. | In multiprocessors systems , cache coherence is always an important issue 在多处理器计算机系统中, cache一致性一直是一个重要的问题。 | | 2. | Dividing the cache into separating tag and data arrays reduces the access time of the cache . in order to keep the cache coherence , ccu adopts moesi protocol Lx ? 1164具有独立的32kb片内数据高速缓存和32kb片内指令高速缓存,通过ccu可以同时对指令cache和数据cache进行查询。 | | 3. | In this paper , we made some analysis on conventional cache coherence protocols . we provide one way to reduce remote access delay - adding a router - cache in routing components 本文首先对常用的cache一致性协议进行了分析,提出了一种在多处理器系统中减少远程访问延时的方式一在路由部件中加入存储部件一路由器cache 。 | | 4. | This policy is novel in the sense that it adopts befitting policies for different network connections with different optimization aims , and provides support for cache coherence upon transition between different situations 该策略在不同网络连接下分别采用更适合的作法,同时考虑了不同连接及断接状态间转换这些特殊情况,并对缓存项视图渐进维护。 | | 5. | Then , we give some description about the working principle , organization , function of router - cache and where it should be . we also gave out a cache coherence protocol for multiprocessors systems with router - caches 本文接着描述了路由器cache的工作原理,对其的组织、在系统中的位置、应有的功能等方面进行了讨论,并设计了含有路由器cache的多处理器系统的cache一致性协议。 | | 6. | Smpdca architecture has six outstanding excellences : complexity of the control logics of smpdca is lower than large scale superscalar ; supplying shortest inter - processor communication latency using the shared li data cache ; no cost to maintain cache coherence ; hit rate of data cache increase ; easy to reuse many softwares of symmetric multiprocessor ( smp ) ; exploit the parallelism of applications from many levels . this paper present the architecture model of smpdca , and illustrated its function units , and discussed its key techniques , and analyzed the address image policy of multi - ported cache Smpdca结构具有六个突出优势:相对于大规模的超标量结构而言, smpdca结构的控制逻辑复杂性明显要低得多;相对于通过共享主存来实现处理器之间的通信的结构而言,通过一个共享的第一级数据cache来实现处理器之间的通信的smpdca结构能够提供非常小的处理器之间的通信延迟;没有cache一致性维护开销;数据cache命中率提高;便于smp (对称多处理器结构)的软件重用;从多个层次上开发程序的并行性。 | | 7. | She has over 14 years of experience in her broad areas of interest , including the design and performance evaluation of memory systems , cache coherence protocols , parallel i o , parallel file systems , java server performance , application server database integration , and linux performance 她在自己感兴趣的广泛领域具有14年多的经验,这其中包括存储系统、高速缓存一致协议、并行i / o 、并行文件系统、 java服务器性能、应用程序服务器数据库集成和linux性能等方面的设计和性能评估。 |
- Similar Words:
- "cache buffer pool" English translation, "cache buffer-pool" English translation, "cache cache" English translation, "cache capacity" English translation, "cache card" English translation, "cache coherency" English translation, "cache coherent" English translation, "cache configuration" English translation, "cache control" English translation, "cache control register" English translation
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